This invention relates generally to master-slave flip-flops and, more particularly, to a master-slave flip-flop having an improved data gate for substantially reducing the possibility of transmitting incorrect data to the slave section due to a race condition in the master section without sacrificing performance speed.
A well known master-slave transistor comprises a data gate having a data input (D.sub.in) for generating internal data signals (D and D), a master section for receiving D and D and a clock signal (C.sub.p) and generating in response thereto first and second signals (A and B) indicative of D.sub.in, and a slave section responsive to A and B for storing the input data and generating the traditional Q and Q outputs. Unfortunately, this flip-flop suffers from several disadvantages. The internal data line or signal D when high is permitted to rise from approximately 2 volts to very near the supply voltage level (typically 5 volts) while D when high rises to only approximately 2.4 volts. This large voltage swing on the internal data line D may produce an adverse race condition in the master section which results in the transmission of incorrect data to the slave section. Furthermore, the high maximum voltage attainable at D causes a high voltage swing which in turn increases the propogation delays and set-up times. Finally, due to the non-symmetric high and low levels attainable on D and D, there is a substantial skew between the time it takes to set a "0" (T.sub.set0) and the time it takes to set a "1" (T.sub.set1).